The present invention claims the benefit of the Korean Patent Application No. P2001-58279 filed in Korea on Sep. 20, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a non-volatile ferroelectric memory, and more particularly, to a column repair circuit in a non-volatile ferroelectric memory having column redundancy.
2. Background of the Related Art
In general, a nonvolatile ferroelectric memory device such as a ferroelectric random access memory (FRAM), for example, has a data processing speed equivalent to that of dynamic random access memory (DRAM), and the nonvolatile ferroelectric memory device retains data during a power OFF state.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having high residual polarization characteristics. The residual polarization characteristics permit the retention of data when an applied electric field is removed.
FIG. 1 illustrates a characteristic curve of a hysteresis loop of a ferroelectric material according to the related art. In FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). The xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states correspond to xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99, respectively.
FIG. 2 illustrates a unit cell of a non-volatile ferroelectric memory according to the related art. In FIG. 2, the unit cell is provided with a bitline B/L formed along one direction, a wordline W/L formed perpendicular to the bitline, a plateline P/L formed spaced from the wordline along a direction identical to the wordline, a transistor T1 having a gate connected to the wordline and a source connected to the bitline B/L, and a ferroelectric capacitor FC1 having a first terminal connected to a drain of the transistor T1 and a second terminal connected to the plateline P/L.
The data input/output operation of the related art non-volatile ferroelectric memory will be explained. FIG. 3A illustrates a timing diagram of a write mode operation of a ferroelectric memory according to the related art, and FIG. 3B illustrates a timing diagram of a read mode operation of the non-volatile ferroelectric memory.
During a writing mode, an external chip enable signal CSBpad transits from a xe2x80x98highxe2x80x99 level to a xe2x80x98lowxe2x80x99 level and, at the same time, an external write enable signal WEBpad transits from a xe2x80x98highxe2x80x99 level to a xe2x80x98lowxe2x80x99 level. When address decoding is started in the write mode, a pulse applied to the wordline transits from a xe2x80x98lowxe2x80x99 level to a xe2x80x98highxe2x80x99 level to select a specific cell. Accordingly, the wordline is held at a xe2x80x98highxe2x80x99 level, the plateline has a xe2x80x98highxe2x80x99 level signal applied thereto for one period and a xe2x80x98lowxe2x80x99 level signal applied thereto for another period in sequence. In order to write a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 to the selected cell, a xe2x80x98highxe2x80x99 or xe2x80x98lowxe2x80x99 level signal synchronized to the write enable signal WEBpad is applied to the bitline. Moreover, if a xe2x80x98highxe2x80x99 level signal is applied to the bitline and a signal applied to the plateline is at a xe2x80x98lowxe2x80x99 level in a period, then a signal applied to the wordline is at a xe2x80x98highxe2x80x99 level state, thereby a logical value xe2x80x981xe2x80x99 is written to the ferroelectric capacitor. If a xe2x80x98lowxe2x80x99 level signal is applied to the bitline, and a signal applied to the plateline is at a xe2x80x98highxe2x80x99 level, then a logical value xe2x80x980xe2x80x99 is written to the ferroelectric capacitor.
The operation for reading the data stored in the cell by the foregoing write mode operation will be explained.
If the chip enable signal CSBpad is transited from a xe2x80x98highxe2x80x99 level to a xe2x80x98lowxe2x80x99 level from outside of the cell, all bitlines are equalized to a xe2x80x98lowxe2x80x99 level voltage by an equalizer signal before the wordline is selected. Then, after the bitlines are disabled, an address is decoded, and the decoded address transits the wordline from a xe2x80x98lowxe2x80x99 level to a xe2x80x98highxe2x80x99 level, to select the cell. A xe2x80x98highxe2x80x99 level signal is applied to the plateline of the selected cell to break a data corresponding to a logical value xe2x80x981xe2x80x99 stored in the ferroelectric memory. If a logical value xe2x80x980xe2x80x99 is stored in the ferroelectric memory, then a data corresponding to the logical value xe2x80x980xe2x80x99 is not broken. The data not broken, and the data broken thus provide values different from each other according to the aforementioned hysteresis loop, so that the sense amplifier senses a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99. That is, when the data broken is a case when the value is changed from xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99 in the hysteresis loop in FIG. 1, and the case of the data not broken is a case when the value is changed from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99 in the hysteresis loop in FIG. 1. Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case of the data broken, a logical value xe2x80x981xe2x80x99 is provided as amplified, and in the case of the data not broken, a logical value xe2x80x980xe2x80x99 is provided as amplified. After the sense amplifier amplifies and provides the data, since an original data should be restored, the plateline is disabled from a xe2x80x98highxe2x80x99 level to a xe2x80x98lowxe2x80x99 level during a state in which a xe2x80x98highxe2x80x99 level signal is applied to the wordline.
FIG. 4 illustrates a block diagram of a non-volatile ferroelectric memory according to the related art. In FIG. 4, the non-volatile ferroelectric memory is provided with a main cell array part 41 having a lower part allocated for a reference cell array part 42, a wordline driver part 43 on one side of the main cell array part 41 for applying a driving signal to the main cell array part 41 and the reference cell array part 42, and a sense amplifier part 44 under the main cell array part 41. The wordline driver part 43 provides a driving signal to a main wordline in the main cell array part 41, and a reference wordline in the reference cell array part 42. The sense amplifier part 44 has a plurality of sense amplifiers each for amplifying a signal received from the bitline or the bitbarline.
The operation of the non-volatile ferroelectric memory will be explained, with reference to FIG. 5. FIG. 5 illustrates a detail of FIG. 4, wherein the main cell array has a folded bitline structure like a DRAM. In FIG. 5, the reference cell array part 42 has a folded bitline structure, and a reference cell wordline and a reference cell plateline formed in a pair. The reference cell wordline and the reference cell plateline pairs are defined as RWL_1/RPL_1, and RWL_2/RPL_2. When a main cell wordline MWL_Nxe2x88x921 and a main cell plateline MPL_Nxe2x88x921 are enabled, the reference cell wordline RWL_1 and the reference cell plateline RPL_1 are enabled, to load a main cell data on the bitline, and a reference cell data on the bitbarline BB/L. When a main cell wordline MWL_N and a main cell plateline MPL_N are enabled, the reference cell wordline RWL_2 and the reference cell plateline RPL_2 are enabled, to load a main cell data on the bitbarline BB/L, and a reference cell data on the bitline B/L. A bitline voltage REF from the reference cell is between B H (High) and B L (Low), both are bitline voltages from the main cell. Therefore, in order to have the reference voltage REF to be between B_H and B_L, the reference cell may be operated by either of two methods.
A first method is storing a logical xe2x80x9c1xe2x80x9d in a capacitor in the reference cell by forming a size of the reference cell capacitor to be smaller than a size of a main cell capacitor. A second method is storing a logical xe2x80x9c0xe2x80x9d in a capacitor in the reference cell by forming a size of the reference cell capacitor to be greater than a size of a main cell capacitor. Thus, the non-volatile ferroelectric memory provides the reference voltage the sense amplifier requires 44 by using the two methods.
FIG. 6 illustrates a sense amplifier according to the related art included in the sense amplifier part in FIG. 4. In FIG. 6, the sense amplifier is an inverter of a latch type, inclusive of two PMOS transistors, and two NMOS transistors. A first PMOS transistor MP1 and a second PMOS transistor MP2 are arranged opposite to each other, with an output terminal of the first PMOS transistor connected to a gate of the second PMOS transistor MP2, and an output terminal of the second PMOS transistor MP2 connected to a gate of the first PMOS transistor MP1. Input terminals of the first, and second PMOS transistors MP1 and MP2 have a SAP signal applied thereto in common. The SAP signal is an enable signal for enabling the first, and second PMOS transistors MP1 and MP2. An output terminal of the first PMOS transistor MP1 is connected to the first NMOS transistor MN1 in series, and an output terminal of the second PMOS transistor MP2 is connected to the second NMOS transistor MN2 in series. An output terminal of the second NMOS transistor MN2 is connected to a gate of the first NMOS transistor MN1, and an output terminal of the first NMOS transistor MN1 is connected to a gate of the second NMOS transistor MN2. The input terminals of the first and second NMOS transistors MN1 and MN2 have an SAN signal applied thereto in common. The SAN signal is a signal for enabling the first or second NMOS transistor MN1 or MN2. Output terminals of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the bitline B_N in common, and output terminals of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to a next bitline B_N+1. Thus, the sense amplifier with outputs connected to the bitlines B_N, and B_N+1 input/output to/from the main cell and the reference cell. Therefore, during a precharge period when the sense amplifier is disabled, all the SAP, SAN, B_N, and B_N+1 signals are in xc2xd Vcc states. Opposite to this, when the sense amplifier is enabled, the SAP signal is pulled-up to a high level, and the SAN signal is pulled-down to a ground voltage level.
However, the non-volatile ferroelectric memory has the following problems. First, provision of a repair circuit for each memory cell requires a large area of the repair circuits. Second, the large repair circuit area is not suitable for high density device packing. Third, structure, and algorithm of the repair circuit are complicated, and the repairing operation delays operation.
Accordingly, the present invention is directed to a column repair circuit in a non-volatile ferroelectric memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a column repair circuit in a non-volatile ferroelectric memory, which is favorable for high density device packing.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a column repair circuit in a non-volatile ferroelectric memory having main columns and redundancy columns includes a data input/output buffer part for data input/output between the non-volatile ferroelectric memory and an external circuit, a failed column coding part for controlling the main columns and the redundancy columns and connected in response to a failed column address signal to one of main input/output lines in the input/output buffer part and redundancy input/output lines, a repair column adjusting circuit part connected to the failed column coding part for providing a redundancy mode control signal, a data bus amplifying part for amplifying data between the main input/output lines and the main columns to control read/write operation, and a redundancy data bus amplifying part for amplifying data between the redundancy input/output lines and the redundancy columns in response to the redundancy mode control signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.